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rev. 1.1 2/08 copyright ? 2008 by silicon laboratories si4710/11 si4710/11-b30 si4710/11-b30 fm r adio t ransmitter features applications description the si4710/11 integrates the complete transmit functi ons for standards- compliant unlicensed fm broadcast stereo transmission. users must comply with local regulations on radio frequency (rf) transmission. functional block diagram integrated receive power measurement worldwide fm band support (76?108 mhz) requires only two external components frequency synthesizer with integrated vco digital stereo modulator programmable pre-emphasis analog/digital audio interface audio silence detector programmable reference clock rds/rbds encoder (si4711 only) pcb loop and stub antenna support with self-calibrated capacitor tuning programmable transmit level audio dynamic range control advanced modulation control 2.7 to 5.5 v supply voltage integrated ldo regulator 3 x 3 x 0.55 mm 20-pin qfn pb-free and rohs compliant designed for compatibility with cellular operation cellular handsets/hands-free mp3 players portable media players wireless speakers/microphone satellite digital audio radios personal computers/notebooks adc adc si4710/11 dsp dac dac vio sclk sdio control interface sen gpo rds ( si4711 ) gpio3/dclk rst gpio2/int gpo1 ldo vdd gnd 2.7?5.5 v c1 22 nf lin rin tx ant txo din dfs afc rclk l1 120 nh rfgnd digital audio patents pending note: to ensure proper operation and performance, follow the guide- lines in ?an383: universal antenna selection and layout guidelines.? silicon laboratories will evaluate schematics and lay- outs for qualified customers. ordering information: see page 32. pin assignments gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 gpo2/int vio rin dfs din gnd rst nc txo rclk sdio vdd nc rfgnd gpo3/dclk nc gpo1 lin sclk sen si4710/11 (top view)
si4710/11-b30 2 rev. 1.1
si4710/11-b30 rev. 1.1 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.1. test circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2. test circuit bill of mate rials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. typical application schemati cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1. analog audio inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2. digital audio inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3. typical application schem atic bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4. universal am/fm rx/fm tx application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.1. universal am/fm rx/fm tx bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.2. fm transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 5.3. digital audio interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4. line input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.5. audio dynamic range control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.6. audio limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 5.7. pre-emphasis and de-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.8. rds/rbds processor (si4711 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.9. tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.10. reference clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.11. control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 5.12. gpo outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.13. reset, powerup, and powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.14. programming wi th commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6. commands and propertie s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7. pin descriptions: si4710/ 11-gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9. package markings (top marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1. si4710 top mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2. si4711 top mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.3. top mark explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10. package outline: si4710/ 11-gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11. pcb land pattern: si4710/ 11-gm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 12. additional reference resour ces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
si4710/11-b30 4 rev. 1.1 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit supply voltage v dd 2.7 ? 5.5 v interface supply voltage v io 1.5 ? 3.6 v power supply powerup rise time v ddrise 10 ? ? s interface supply powerup rise time v iorise 10 ? ? s ambient temperature t a ?20 25 85 c note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at v dd = 3.3 v and 25 c unless otherwise stated. parameters are tested in production unless otherwise stated. table 2. absolute maximum ratings 1,2 parameter symbol value unit supply voltage v dd ?0.5 to 5.8 v interface supply voltage v io ?0.5 to 3.9 v input current 3 i in 10 ma input voltage 3 v in ?0.3 to (v io + 0.3) v operating temperature t op ?40 to 95 c storage temperature t stg ?55 to 150 c rf input level 4 0.4 v pk notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data shee t. exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. the si4710/11 devices are high-performance rf integrated ci rcuits with certain pins having an esd rating of < 2 kv hbm. handling and assembly of these devices sh ould only be done at esd-protected workstations. 3. for input pins sclk, sen, sdio, rst, rclk, dclk, dfs, din, gpo1, gpo2/int , and gpo3. 4. at rf input pin, txo.
si4710/11-b30 rev. 1.1 5 table 3. dc characteristics test conditions: v rf = 118 dbv, stereo, f = 68.25 khz, fpilot = 6.75 khz, refclk = 32.768 khz, unless otherwise specified. production test conditions: v dd = 3.3 v, v io = 3.3 v, t a = 25 c, f rf = 98 mhz. characterization test conditions: v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c, f rf = 76?108 mhz. parameter symbol test condition min typ max unit fm transmitter from line input tx supply current i tx ? 18.8 22.8 ma tx interface supply current i io ?320600a fm transmitter from digital audio input tx supply current i dtx dclk = 3.072 mhz ? 18.3 ? ma tx interface supply current i dio dclk = 3.072 mhz ? 320 ? a supplies and interface v dd powerdown current i dd powerdown mode ? 10 20 a v io interface powerdown current i io sclk, rclk inactive powerdown mode ?310a high level input voltage 1 v ih 0.7 x v io ? v io +0.3 v low level input voltage 1 v il ?0.3 ? 0.3 x v io v high level input current 1 i ih v in = v io =3.6v ?10 ? 10 a low level input current 1 i il v in =0v, v io =3.6v ?10 ? 10 a high level output voltage 2 v oh i out = 500 a 0.8 x v io ??v low level output voltage 2 v ol i out =?500a ? ? 0.2x v io v notes: 1. for input pins sclk, sen, sdio, rst, rclk, dclk, dfs, din, gpo1, gpo2/int , and gpo3. 2. for output pins sdio, gpo1, gpo2/int , and gpo3.
si4710/11-b30 6 rev. 1.1 figure 1. reset timing parameters for busmode select table 4. reset timing characteristics 1,2,3 (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol min typ max unit rst pulse width and gpo1, gpo2/int setup to r st 4 t srst 100 ? ? s gpo1, gpo2/int hold from r st t hrst 30 ? ? ns important notes: 1. when selecting 2-wire mode, the user must ensure that a 2- wire start condition (falling edge of sdio while sclk is high) does not occur within 300 ns before the rising edge of rst . 2. when selecting 2-wire mode, the user must ensure t hat sclk is high during the rising edge of rst , and stays high until after the 1st start condition. 3. when selecting 3-wire or spi modes, the user must ensure th at a rising edge of sclk does not occur within 300 ns before the rising edge of rst . 4. if gpo1 and gpo2 are actively driven by the user, then minimum t srst is only 30 ns. if gpo1 or gpo2 is hi-z, then minimum t srst is 100 s, to provide time for on-chip 1 m devices (active while rst is low) to pull gpo1 high and gpo2 low. 70% 30% gpo1 70% 30% gpo2/ int 70% 30% t srst rst t hrst
si4710/11-b30 rev. 1.1 7 table 5. 2-wire control interface characteristics 1,2,3 (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk frequency f scl 0?400khz sclk low time t low 1.3 ? ? s sclk high time t high 0.6 ? ? s sclk input to sdio setup (start) t su:sta 0.6 ? ? s sclk input to sdio hold (start) t hd:sta 0.6 ? ? s sdio input to sclk setup t su:dat 100 ? ? ns sdio input to sclk hold 4,5 t hd:dat 0?900ns sclk input to sdio setup (stop) t su:sto 0.6 ? ? s stop to start time t buf 1.3 ? ? s sdio output fall time t f:out ?250ns sdio input, sclk rise/fall time t f:in t r:in ?300ns sclk, sdio capacitive loading c b ??50pf input filter pu lse suppression t sp ? ? 50 ns notes: 1. when v io = 0 v, sclk and sdio are low-impedan ce. 2-wire control interface is i 2 c compatible. 2. when selecting 2-wire mode, the user must ensure that a 2- wire start condition (falling edge of sdio while sclk is high) does not occur within 300 ns before the rising edge of rst . 3. when selecting 2-wire mode, the user must ensure th at sclk is high during the rising edge of rst , and stays high until after the first start condition. 4. the si4710/11 delays sdio by a minimum of 300 ns from the v ih threshold of sclk to comply with the minimum t 5. hd:dat specification. 6. the maximum t hd:dat has only to be met when f scl = 400 khz. at frequencies below 400 khz, t hd:dat may be violated as long as all other timing parameters are met. 20 0.1 c b 1 pf ----------- - + 20 0.1 c b 1 pf ----------- - +
si4710/11-b30 8 rev. 1.1 figure 2. 2-wire control interface read and write timing parameters figure 3. 2-wire control interface read and write timing diagram sclk 70% 30% sdio 70% 30% start start stop t f:in t r:in t low t high t hd:sta t su:sta t su:sto t sp t buf t su:dat t r:in t hd:dat t f:in, t f:out sclk sdio start stop address + r/w ack data ack data ack a6-a0, r/w d7-d0 d7-d0
si4710/11-b30 rev. 1.1 9 figure 4. 3-wire control interface write timing parameters figure 5. 3-wire control interface read timing parameters table 6. 3-wire control interface characteristics (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk frequency f clk 0?2.5mhz sclk high time t high 25 ? ? ns sclk low time t low 25 ? ? ns sdio input, sen to sclk setup t s 20 ? ? ns sdio input to sclk hold t hsdio 10 ? ? ns sen input to sclk hold t hsen 10 ? ? ns sclk to sdio output valid t cdv read 2 ? 25 ns sclk to sdio output high z t cdz read 2 ? 25 ns sclk, sen , sdio, rise/fall time t r t f ? ? 10 ns note: when selecting 3-wire mode, the user must ensure that a rising edge of sclk does not occur within 300 ns before the rising edge of rst . sclk 70% 30% sen 70% 30% sdio a7 a0 70% 30% t s t s t hsdio t hsen a6-a5, r/w, a4-a1 address in data in d15 d14-d1 d0 t high t low t r t f ? cycle bus turnaround sclk 70% 30% sen 70% 30% sdio 70% 30% t hsdio t cdv t cdz address in data out a7 a0 a6-a5, r/w, a4-a1 d15 d14-d1 d0 t s t s t hsen
si4710/11-b30 10 rev. 1.1 figure 6. spi control interface write timing parameters figure 7. spi control interface read timing parameters table 7. spi control interface characteristics (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c) parameter symbol test condition min typ max unit sclk frequency f clk 0?2.5mhz sclk high time t high 25 ? ? ns sclk low time t low 25 ? ? ns sdio input, sen to sclk setup t s 15 ? ? ns sdio input to sclk hold t hsdio 10 ? ? ns sen input to sclk hold t hsen 5??ns sclk to sdio output valid t cdv read 2 ? 25 ns sclk to sdio output high z t cdz read 2 ? 25 ns sclk, sen , sdio, rise/fall time t r, t f ? ? 10 ns note: when selecting spi mode, the user must ensure that a rising edge of sclk d oes not occur within 300 ns before the rising edge of rst . sclk 70% 30% sen 70% 30% sdio c7 c0 70% 30% t s c6 ?c1 control byte in 8 data bytes in d7 d6 ?d1 d0 t s t hsdio t high t low t hsen t f t r bus turnaround sclk 70% 30% sen 70% 30% sdio 70% 30% t hsdio control byte in c7 c0 c6 ?c1 t s t hsen t s t cdz t cdv 16 data bytes out (sdio or gpo1) d7 d6 ?d1 d0
si4710/11-b30 rev. 1.1 11 figure 8. digital audio interface timing parameters, i 2 s mode table 8. digital audio interface characteristics (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a =?20 to 85c) parameter symbol test condition min typ max unit dclk pulse width high t dch 10 ? ? ns dclk pulse width low t dcl 10 ? ? ns dfs set-up time to dclk rising edge t su:dfs 5?? ns dfs hold time from dclk rising edge t hd:dfs 5?? ns din set-up time from dclk rising edge t su:din 5??ns din hold time from dclk rising edge t hd:din 5??ns dclk, dfs, din, rise/fall time t r t f ? ? 10 ns dclk tx frequency 1,2 1.0 ? 40.0 mhz notes: 1. guaranteed by characterization. 2. the dclk frequency may be set below the minimum specificat ion if digital_input_sample_rate is first set to 0 (disable). dclk dfs din t su:din t su:dfs t hd:din t hd:dfs t f t r
si4710/11-b30 12 rev. 1.1 table 9. fm transmitter characteristics 1 (test conditions: v rf = 118 dbv, stereo, f = 68.25 khz, fpilot = 6.75 khz, refclk = 32.768 khz, 75 s pre-emphasis, unless otherwise specified. production test conditions: v dd = 3.3 v, v io = 3.3 v, t a = 25 c, f rf = 98 mhz. characterization test conditions: v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c, f rf = 76?108 mhz. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at v dd = 3.3 v and 25 c unless otherwise stated. parameters are tested in product ion unless otherwise specified.) parameter symbol test condition min typ max unit transmit frequency range 2 f rf 76 ? 108 mhz transmit frequency accuracy and stability 2,3 ?3.5 ? 3.5 khz transmit voltage accuracy 2 v rf = 103?117 dbv ?2.5 ? 2.5 db transmit voltage accuracy v rf = 102, 118 dbv ?2.5 ? 2.5 db transmit voltage temperature coefficient 2 ?0.075 ? ?0.025 db/oc transmit channel edge power > 100 khz, pre-emphasis off ???20dbc transmit adjacent channel power > 200 khz, pre-emphasis off ??30?26 dbc transmit alternate channel power > 400 khz, pre-emphasis off ??30?26 dbc transmit emissions in-band (76?108 mhz) ? ? ?30 dbc output capacitance max 2 c tune ?53? pf output capacitance min 2 c tune ?5? pf pre-emphasis time constant 2 tx_premphasis = 75 s 70 75 80 s tx_premphasis = 50 s 45 50 54 s audio snr mono 2 f = 22.5 khz, mono, limiter off 58 63 ? db audio snr stereo f = 22.5 khz, fpilot = 6.75 khz, stereo, limiter off 53 58 ? db audio thd mono f = 75 khz, mono, limiter off ?0.10.5 % audio thd stereo 2 f = 22.5 khz, fpilot = 6.75 khz, stereo, limiter off ?0.10.5 % audio stereo separation 2 left channel only 30 35 ? db notes: 1. fm transmitter performance specifications are subject to adherence to silicon laboratories guidelines in ?an383: universal antenna selection and layout guidelines.? silic on laboratories will evaluate schematics and layouts for qualified customers. tested with test schematic (l = 120 nh, q > 30) shown in figure 9 on page 14. 2. guaranteed by characterization. 3. no measurable frf/ v dd at v dd of 500 mvpk-pk at 100 hz to 10 khz.
si4710/11-b30 rev. 1.1 13 sub carrier rejection ratio scr 40 50 ? db powerup settling time 2 ??110ms input signal level 2 v ai ? ? 0.636 v pk frequency flatness 2 mono, 1.5 db, f = 75 khz, 0, 50, 75 s pre-emphasis, limiter off 30 ? 15 k hz high pass corner frequency 2 mono, ?3 db, f = 75 khz, 0, 50, 75 s pre-emphasis, limiter off 5?30hz low pass corner frequency 2 mono, ?3 db, f = 75 khz, 0, 50, 75 s pre-emphasis, limiter off 15 k ? 16 k hz audio imbalance mono ?1 ? 1 db pilot modulation rate accuracy 2 f=68.25khz, fpilot = 6.75 khz, stereo ?10 ? 10 % audio modulation rate accuracy 2 f=68.25khz, fpilot = 6.75 khz, stereo ?10 ? 10 % input resistance 2 liatten[1:0] = 11 50 60 ? k input capacitance 2 ?10? pf table 10. reference clock characteristics (v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c, f rf = 76?108 mhz) supported parameter symbol test condition min typ max unit rclk frequency range 1,2 31.130 32.768 40,000 khz frequency tolerance 1 ?50 ? 50 ppm notes: 1. guaranteed by characterization. 2. the rclk frequency divided by an integer number (the prescale r value) must fall in the range of 31,130 to 34,406 hz. therefore, the range of rclk frequencies is not continuous below frequencies of 311.3 khz. table 9. fm transmitter characteristics 1 (continued) (test conditions: v rf = 118 dbv, stereo, f = 68.25 khz, fpilot = 6.75 khz, refclk = 32.768 khz, 75 s pre-emphasis, unless otherwise specified. production test conditions: v dd = 3.3 v, v io = 3.3 v, t a = 25 c, f rf = 98 mhz. characterization test conditions: v dd = 2.7 to 5.5 v, v io = 1.5 to 3.6 v, t a = ?20 to 85 c, f rf = 76?108 mhz. all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at v dd = 3.3 v and 25 c unless otherwise stated. parameters are tested in product ion unless otherwise specified.) parameter symbol test condition min typ max unit notes: 1. fm transmitter performance specifications are subject to adherence to silicon laboratories guidelines in ?an383: universal antenna selection and layout guidelines.? silic on laboratories will evaluate schematics and layouts for qualified customers. tested with test schematic (l = 120 nh, q > 30) shown in figure 9 on page 14. 2. guaranteed by characterization. 3. no measurable frf/ v dd at v dd of 500 mvpk-pk at 100 hz to 10 khz.
si4710/11-b30 14 rev. 1.1 2. test circuit 2.1. test ci rcuit schematic figure 9. test circuit schematic 2.2. test circuit bill of materials table 11. si4710/11 test circuit bill of materials component(s) value/description supplier(s) c1 supply bypass capacitor, 22 nf, 20%, z5u/x7r murata c2, c3 ac coupling capacitor, 0.47 f murata c4 2 pf, .05 pf, 06035jzr0ab avx l1 120 nh inductor, qmin = 30 murata r1 49.9 , 5% murata u1 si4710/11 fm radio tran smitter silicon laboratories 0.47 f 0.47 f c4 r1 20 19 18 17 16 u1 si4710/11 nc nc rfgnd txo rst rin dfs din gnd v dd nc gpo1 gpo2/int gpo3/dclk lin sen sclk sdio rclk v io sen sclk sdio 1 2 3 4 5 15 14 13 12 11 6 7 8 9 10 rst rclk c1 vbattery 2.7 to 5.5 v v io 1.5 to 3.6 v lin rin l1 120 nh 2 pf 22 nf v io 50 v txout c2 c3 notes: 1. si4710/11 is shown configured in i 2 c compatible bus mode. 2. gpo2/int can be configured for interrupts with the powerup command. 3. to ensure proper operation and fm transmitter performance, follow the guidelines in ?an383: 3 mm x 3 mm qfn universal layout guide.? silicon laboratories will evaluate schematics and layouts for qualified customers. 4. lin, rin line inputs must be ac-coupled.
si4710/11-b30 rev. 1.1 15 3. typical application schematics 3.1. analog audio inputs figure 10. analog audio inputs (lin, rin) 20 19 18 17 16 u1 si4710/11 nc nc rfgnd txo rst rin dfs din gnd v dd nc gpo1 gpo2/int gpo3/dclk lin sen sclk sdio rclk v io sen sclk sdio 1 2 3 4 5 15 14 13 12 11 6 7 8 9 10 rst rclk c1 vbattery 2.7 to 5.5 v v io 1.5 to 3.6 v lin rin tx antenna l1 120 nh 22 nf v io notes: 1. si4710/11 is shown configured in i 2 c compatible bus mode. 2. gpo2/int can be configured for interrupts with the powerup command. 3. to ensure proper operation and fm transmitter performance, follow the guidelines in ?an383: 3 mm x 3 mm qfn universal layout guide.? silicon laboratories will evaluate schematics and layouts for qualified customers. 4. lin, rin line inputs must be ac-coupled. c2 c3 0.47 f 0.47 f
si4710/11-b30 16 rev. 1.1 3.2. digital audio inputs figure 11. digital audio inputs (din, dfs, dclk) 3.3. typical application schematic bill of materials table 12. si4710/11 bill of materials component(s) value/description supplier(s) c1 supply bypass capacitor, 22 nf, 20%, z5u/x7r murata c2, c3 ac coupling capacitor, 0.47 f murata l1 120 nh inductor, qmin = 30 murata r1, r2 2 k resistor any r3 600 resistor any u1 si4710/11 fm radio tran smitter silicon laboratories 20 19 18 17 16 u1 si4710/11 nc nc rfgnd txo rst rin dfs din gnd v dd nc gpo1 gpo2/int gpo3/dclk lin sen sclk sdio rclk v io sen sclk sdio 1 2 3 4 5 15 14 13 12 11 6 7 8 9 10 rst rclk c1 din vbattery 2.7 to 5.5 v v io 1.5 to 3.6 v dclk dfs tx antenna l1 120 nh 22 nf v io notes: 1. si4710/11 is shown configured in i 2 c compatible bus mode. 2. gpo2/int can be configured for interrupts with the powerup command. 3. to ensure proper operation and fm transmitter performance, follow the guidelines in ?an383: si47xx 3 mm x 3 mm qfn universal layout guide.? silicon laboratories will evaluate schematics and layouts for qualified customers. r1 r2 r3
si4710/11-b30 rev. 1.1 17 4. universal am/fm rx/fm tx application schematic figure 12 shows an application schematic that sup ports the si47xx family of 3 mm x 3 mm qfn products, including the si4702/3/4/5 fm receivers, si471x fm tr ansmitters, si472x fm transceivers, and si473x am/fm receivers. figure 12. universal am/fm rx/fm tx application schematic following the schematic and layout recommendations detailed in ?an383: universal antenna selection and layout guidelines ? will result in optimal performance with the minimal application schema tic shown in figure 12. ?universal am/fm rx/fm tx application schematic?. system component s are those that are likely to be present for any tuner or transmitter design. c4 1 nf l headphone 270 nh system component 20 19 18 17 16 u1 si47xx nc fmi rfgnd txo/ami rst gnd/rin/dout lout/dfs rout/din gnd vdd nc gpo1 gpo2/irq gpo3/dclk lin/dfs sen sclk sdio rclk vio 1 2 3 4 5 15 14 13 12 11 6 7 8 9 10 c1 vbattery 2.7 to 5.5 v lin l short 120 nh 22 nf r12 0 gpio1 gpio3 gpio2 r13 0 vbattery 2.7 to 5.5 v si4702/03: populate r12, r13, r21, c14, and c15 si4704/05/1x/2x/3x analog: populate c7, c8, c14 and c15 as shown si4704/05/1x/2x/3x digital: populate r16, r17, r18, r19, and r20 as shown c14/r19 0.39 uf/ 0 sen sclk sdio rst rclk vio c15/r20 0.39 uf/ 0 c7/r17 0.39 uf/ 2 k rin c8/r18 0.39 uf/ 600 system components c17/r21 3.3pf/0 l ferrite 180? 600 uh fb1 2.5 k @ 100 mhz fb2 2.5 k @ 100 mhz hp jack j1 s 1 r 2 t 5 right audio left audio u2 headphone amplifier system component r14 0 r16 2 k c16 470 nf fm embedded rx/tx antenna am ferrite antenna system component l1 10 nh system component d5 d4 d3
si4710/11-b30 18 rev. 1.1 4.1. universal am/fm rx/f m tx bill of materials the bill of materials for the expanded application schematic shown in figu re 12 is provided in table 13. refer to the individual device layout guides and antenna interf ace guides for a discussion of the purpose of each component. table 13. bill of materials designator description note c1 supply bypass capacitor, 22 nf, 10%, z5u/x7r, 0402 u1 silicon laboratories si47xx, 3 mm x 3 mm, 20 pin, qfn r12, r13, r19, r20, r21 0 jumper, 0402 r12, r13, and r21 for si4702/03 only c16 am antenna ac coupling capacitor, 470 nf, 20%, z5u/x7r am ferrite antenna lferrite am ferrite loop stick, 180?600 h am ferrite antenna fb1,fb2 ferrite bead, 2.5 k @ 100 mhz, 0603, murata blm18bd252sn1d headphone antenna lheadphone headphone antenna matching inductor, 270 nh, 0603, q>15, murata lqw18anr27j00d headphone antenna lshort embedded antenna matching inductor, 120 nh, 0603, q>30, murata lqw18anr12j00d embedded antenna r14 embedded antenna jumper, 2.2 , 0402 optional c2 supply bypass capacitor, 22 nf, 10%, z5u/x7r, 0402 optional c3 supply bypass capacitor, 100 nf, 10%, z5u/x7r, 0402 optional c5, c6 headphone amp output shunt capacitor, 100 pf, 10%, z5u/x7r, 0402 optional r7-r11 current limiting resistor, 20 ?2 k , 0402 optional c12, c13 crystal load capaci tor, 22 pf, 5%, cog optional x1 crystal, epson fc-135 optional c7, c8 si47xx input ac coupling capacitor, 0.39 f, x7r/x5r, 0402 system component d1-d5 esd diode, sot23-3, california mi cro devices cm1214-01st system component c11 supply bypass capacitor, 100 nf, 10%, z5u/x7r, 0402 headphone amplifier c4 headphone antenna ac coupling capacitor, 1 nf, 10%, z5u/x7r, 0402 headphone antenna c9, c10 headphone amp output ac coupling capacitor, 125 uf, x7r, 0805 headphone amplifier c14, c15 headphone amp input ac coupling capacitor, 0.39 f, x7r/x5r, 0402 headphone amplifier r1,r2,r3,r4 headphone amp feedback/gain resistor, 20 k , 0402 headphone amplifier r5, r6 headphone amp bleed resistor, 100 k , 0402 headphone amplifier u2 headphone amplifier, national semiconductor, lm4910ma headphone amplifier r16, r17 current limiting resistor, 2 k , 0402 system component r18 current limiting resistor, 600 , 0402 system component l1 vco filter inductor, 10 nh, 0603, q > 30, murata, lqw18anr01j00d optional c17 vco filter capacitor, 3.3 pf, 0402, cog, venkel, c0402cog2503r3jn optional
si4710/11-b30 rev. 1.1 19 5. functional description 5.1. overview figure 13. functional block diagram the si4710/11 is the first 100% cmos fm radio transmitter with integrated receive functionality to measure received signal strength. the device leverages silicon labs? highly successf ul and proven si4700/01 fm receiver patent family and offers unmatched integration and performance, allowing fm transmit to be added to any portable device with a single chip. the si4710/11 offers industry-lea ding size, performance, low power consumption, flex ibility, and ease of use. the si4710/11?s digital integration reduces the required external components of traditional offerings, resulting in a solution requiring only an external inductor and bypass capacitor, and pcb space of approximately 15 mm 2 . this increases the device reliability and simplifies the design and manufacturing for companies adopting this technology. the si4710/11 performs fm modulation in the digital domain to achieve high fidelity, optimal performance versus power consumption, and flexibility of design. the onboard dsp provides modulation adjustment and audio dynamic range control for optimum sound quality. the si4711 supports the european radio data system (rds) and the us radio broadcast data system (rbds) including all the symbol encoding, block synchronization, and error correction functions. using this feature, the si4711 enables data such as artist name and song title to be transmitted to an rds/rbds receiver. the transmit output (txo) connects directly to the transmit antenna with only one external inductor to provide harmonic filtering. the output is programmable over a 10 db voltage range in 1 db steps. the txo output pin can also be configured for loop antenna support. users are responsible for complying with local regulations on rf transmission (fcc, etsi, arib, etc.). the digital audio interface operates in slave mode and supports a variety of msb-first audio data formats including i 2 s and left-justified modes. the interface has three pins: digital data input (din), digital frame synchronization input (dfs), and a digital bit synchronization input clock (dclk). the si4710/11 supports a number of industry-standard sampling rates including 32, 40, 44.1, and 48 khz. the digital audio interface enables low-power operation by eliminating the need for redundant dacs and adcs on the audio baseband processor. the si4710/11 includes a low-noise stereo line input adc adc si4710/11 dsp dac dac control interface gpo rds (si4711) ldo vdd gnd lin rin tx ant txo afc l1 120 nh rfgnd gpo3/ int gpo1 2.7?5.5 v c1 22 nf dclk gpo2/ sen sclk sdio rst vio rclk dfs din digital audio
si4710/11-b30 20 rev. 1.1 (lin/rin) with programmable attenuation. to ensure optimal audio performanc e, the si4710/11 has a transmit line input property that allows the user to specify the peak amplitude of the analog input required to reach maximum deviation level. the deviation levels of the audio, pilot, and rds/rbds signals can be independently programmed to customize fm transmitter designs. the si4710/11 has a programmable low audio level and high audio level indicators that allows the user to selectively enable and disable the carrier based on the presence of audio content. in addition, the device provides an overmodulation indicator to allow the user to dynamically set the maximum deviation level. the si4710/11 has a programmable audio dynamic range control that can be used to reduce the dynamic range of the audio input signal and increase the volume at the receiver. these features ca n dramatically improve the end user?s listening experience. the si4710/11 is reset by applying a logic low on the rst pin. this causes all register values to be reset to their default values. the digital input/output interface supply (v io ) provides voltage to the rst, sen, sdio, rclk, din, dfs, and dclk pins and can be connected to the audio baseband processor's supply voltage to save power and remove the need for voltage level translators. rclk is not required for register operation. the si4710/11 reference clock is programmable, supporting many rclk inputs as shown in table 9. the si4710/11 are part of a family of broadcast audio solutions offered in standard, 3 x 3 mm 20-pin qfn packages. all solutions are layout compatible, allowing a single pcb to accommodate various feature offerings. the si4710/11 includes line inputs to the on-chip analog-to-digital converters (adc), a programmable reference clock input, and a configurable digital audio interface. the chip supports i 2 c-compliant 2-wire, 8-bit spi, and a 3-wire control interface. 5.2. fm transmitter the transmitter (tx) integr ates a stereo audio adc to convert analog audio signals to high fidelity digital signals. alternatively, digital audio signals can be applied to the si4710/11 directly to reduce power consumption by eliminating the need to convert audio baseband signals to analog and back again to digital. digital signal processing is used to perform the stereo mpx encoding and fm modulation to a low digital if. transmit baseband filters suppress out-of-channel noise and images from the digital low-if signal. a quadrature single-sideband mixer up-converts the digital if signal to rf, and internal rf filters suppress noise and harmonics to support the harmonic emission requirements of cellular phones, gps, wlan, and other wireless standards. the txo output has over 10 db of output level control, programmable in approximately 1 db steps. this large output range enables a variet y of antennas to be used for transmit, such as a monopole stub antenna or a loop antenna. the 1 db step size provides fine adjustment of the output voltage. the txo output requires only one external 120 nh inductor. the inductor is used to resonate the antenna and is automatically calibra ted within the integrated circuit to provide the optimum output level and frequency response for supported transmit frequencies. users are responsible for adjusting their system?s radiated power levels to co mply with local regulations on rf transmission (fcc, etsi, arib, etc.).
si4710/11-b30 rev. 1.1 21 5.3. digital audio interface the digital audio interface operates in slave mode and supports 3 different audio data formats: 1. i 2 s 2. left-justified 3. dsp mode 5.3.1. audio data formats in i 2 s mode, the msb is captured on the second rising edge of dclk following each dfs transition. the remaining bits of the word are sent in order, down to the lsb. the left channel is transferred first when the dfs is low, and the right chan nel is transferred when the dfs is high. in left-justified mode, the msb is captured on the first rising edge of dclk following each dfs transition. the remaining bits of the word are sent in order, down to the lsb. the left channel is transferred first when the dfs is high, and the right channel is transferred when the dfs is low. in dsp mode, the dfs becomes a pulse with a width of 1 dclk period. the left channel is transferred first, followed right away by the rig ht channel. there are two options in transferring the digital audio data in dsp mode: the msb of the left channel can be transferred on the first rising edge of dcl k following the dfs pulse or on the second rising edge. in all audio formats, depend ing on the word size, dclk frequency and sample rates, there may be unused dclk cycles after the lsb of each word before the next dfs transition and msb of the next word. the number of audio bits can be configured for 8, 16, 20, or 24 bits. 5.3.2. audio sample rates the device supports a number of industry-standard sampling rates including 32, 40, 44.1, and 48 khz. the digital audio interface enables low-power operation by eliminating the need for redundant dacs and adcs on the audio baseband processor. the sampling rate is selected using the digital_input_sample_rate property. the device supports dclk frequencies above 1 mhz. after powerup the digi tal_input_sample_rate property defaults to 0 (disabled). after dclk is supplied, the digital_input_sample_rate property should be set to the desired audio sample rate such as 32, 40, 44.1, or 48 khz. the digital_input_sample_rate property must be set to 0 before dclk is removed or the dclk frequency drops below 1 mhz. a device reset is required if this requirement is not followed.
si4710/11-b30 22 rev. 1.1 figure 14. i 2 s digital audio format figure 15. left-justified digital audio format figure 16. dsp digital audio format left channel right channel 1 dclk 1 dclk 13 2n n-1 n-2 13 2n n-1 n-2 lsb msb lsb msb dclk din/dout dfs inverted dclk (ifall = 1) (ifall = 0) i2s (imode = 0000) left channel right channel 13 2n n-1 n-2 13 2 n n-1 n-2 lsb msb lsb msb dclk din/dout dfs inverted dclk (ifall = 1) (ifall = 0) left-justified (imode = 0110) 13 2n n-1 n-2 n n-1 n-2 lsb msb lsb msb dclk din/dout (msb at 1 st rising edge) dfs 13 2 left channel right channel 1 dclk (ifall = 0) (imode = 1100) 13 2n n-1 n-2 n n-1 n-2 lsb msb lsb msb 13 2 left channel right channel din/dout (msb at 2 nd rising edge) (imode = 1000)
si4710/11-b30 rev. 1.1 23 5.4. line input the si4710/11 provides left and right channel line inputs (lin and rin). the inputs are high-impedance and low- capacitance, suited to rece iving line level signals from external audio baseband processors. both line inputs are low-noise inputs with programmable attenuation. passive and active anti-aliasing filters are incorporated to prevent high frequencies from aliasing into the audio band and degrading performance. to ensure optimal audio performance, the si4710/11 has a tx_line_input_level pr operty that allows the user to specify the peak amplitude of the analog input (lilevel[9:0]) required to reach the maximum deviation level programmed in the audio deviation property, tx_audio_deviation. a corresponding line input attenuation code, liatten[1:0], is also selected by the expected peak amplitude level. table 14 shows the line attenuation codes. the line attenuation code is chosen by picking the lowest peak input voltage in table 14 that is just above the expected peak input voltage coming from the audio baseband processor. for exam ple, if the expected peak input voltage from the audio baseband processor is 400 mv, the user chooses liatten[1:0] = 10 since the peak input voltage of 416 mv associated with liatten[1:0] = 10 is just greater than the expected peak input voltage of 400 mv. the user also enters 400 mv into the lilevel[9:0 ] to associate this input level to the maximum fr equency deviation level programmed into the audio deviation property. note that selecting a particular value of liatten[1:0] changes the input resistance of the lin and rin pins. this feature is used for cases where the expected peak input level exceeds the maximum in put level of the lin and rin pins. the maximum analog input level is 636 mvpk. if the analog input level from the audio baseband processor exceeds this voltage, series resistors must be inserted in front of the lin and rin pins to attenuate the voltage such that it is within the allowable operating range. for example, if the audio baseband's expected peak amplitude is 900 mv and the v io supply voltage is 1.8 v, the designer can use 30 k series resistors in front of the lin and rin pins and se lect liatten[1:0] = 11. the resulting expected peak input voltage at the lin/rin pins is 600 mv, since this is just a voltage divider between the lin/rin input resistance (see table 14, 60 k for this example) and the external resistor. note that the peak input voltage corresponding to the chosen liatten[1:0] code still needs to satisfy the condition of being just greater than the attenuated voltage. in this example, a line attenuation code of liatten[1:0] = 11 has a peak input voltage of 636 mv, which is just greater than the expected peak attenuated voltage of 600 mv. also, the expected peak attenuated voltage is entered into the li level[9:0] parameter. again, in this example, 600 mv is entered into lilvevel[9:0]. this example shows one possible solution, but many other solutions exist. the optimal solution is to apply the largest possible voltage to the lin and rin pins for signal-to-noise considerations; however, practical resistor values may limit the choices. note that the tx_line_ input_level parameter will affect the high-pass filter characteristics of the ac- coupling capacitors and the resistance of the audio inputs. the si4710/11 has a programmable low audio level and high audio level indicators that allows the user to selectively enable and disable the carrier based on the presence of audio content. the tx_asq_level_low and tx_asq_level_high pa rameters set the low level and high level threshol ds in dbfs, respectively. the time required for the audio level to be below the low threshold is set with the tx_asq_duration_low parameter, and similarly, the time required for the audio level to be above the high threshold is set with the tx_asq_duration_high parameter. table 14. line attenuation codes liatten[1:0] peak input voltage [mv] rin/lin input resistance [k ] 00 190 396 01 301 100 10 416 74 11 636 60
si4710/11-b30 24 rev. 1.1 5.5. audio dyna mic range control the si4710/11 includes digital audio dynamic range control with programmable gain, threshold, attack rate, and release rate. the total dynamic range reduction is set by the gain value and the audio output compression above the threshold is equal to threshold/(gain + threshold) in db. the gain specified cannot be larger than the absolute value of the threshold. this feature can also be disabled if audio compression is not desired. the audio dynamic range control can be used to reduce the dynamic range of the audio signal, which improves the listening experience on the fm receiver. audio dynamic range reduction increases the transmit volume by decreasing the peak ampl itudes of audio signals and increasing the root mean square content of the audio signal. in other words, it amplifies signals below a threshold by a fixed gain and compresses audio signals above a threshold by the ratio of threshold/(gain + threshold). figure 17 shows an example transfer function of an audio dynamic range controller with the threshold set at ?40 dbfs and a gain = 20 db relative to an uncompressed transfer function. figure 17. audio dynamic range transfer function for input signals below the threshold of ?40 dbfs, the output signal is amplified or gained up by 20 db relative to an uncompressed signal. audio inputs above the threshold are compressed by a 2 to 1 db ratio, meaning that every 2 db increase in audio input level above the threshold results in an audio output increase of 1 db. in this example, the input dynamic range of 90 db is reduced to an output dynamic range of 70 db. figure 18 shows the time doma in characteristics of the audio dynamic range controller. the attack rate sets the speed with which the audio dynamic range controller responds to changes in the input level, and the release rate sets the speed with which the audio dynamic range controller returns to no compression once the audio input level drops below the threshold. figure 18. time domain characteristics of the audio dynamic range controller 5.6. audio limiter the si4710/11 also includes a digital audio limiter. the audio limiter prevents over-modulation of the fm transmit output by dynamically attenuating peaks in the audio input signal that exceed a programmable threshold. the limiter threshold is set to the programmed audio deviation + ten percent. the threshold ensures that the output signal audio deviation does not exceed the programmed levels, avoiding audible artifacts or distortion in the target fm receiver, and complying with fcc or etsi regulatory standards. the limiter performs as a peak detector with an attack rate set to one audio sample, resulting in an almost immediate attenuation of the input peak. the recover rate is programmable to the customer?s preference, and is set by default to 5 ms. this is the recommended setting to avoid audible pumping or popping. please refer to ?an332: universal programming guide.? 0 ?10 ?20 ?30 ?40 ?50 ?60 input [dbfs] ?70 output [dbfs] threshold = ?40 db m = 1 ?80 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?90 m = 1 gain = 20 db compression 2:1 db no compression attack time threshold release time audio input audio output
si4710/11-b30 rev. 1.1 25 5.7. pre-emphasi s and de-emphasis pre-emphasis and de-emphasis is a technique used by fm broadcasters to improve the signal-to-noise ratio of fm receivers by reducing the effects of high-frequency interference and noise. when the fm signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. all fm receivers incorporate a de-emphasis f ilter that attenuates high frequencies to restore a flat frequency response. two time constants are used in various regions. the pre- emphasis time constant is programmable to 50 or 75 s and is set by using the tx_preemphasis property. 5.8. rds/rbds pro cessor (si4711 only) the si4711 implements an rds/rbds* processor for symbol encoding, block synchronization, and error correction. digital data can be transmitted with the si4711 rds/rbds encoding feature. rds transmission is supported with three different modes. the first mode is the simplest mode and requires no additional user support except for pre- loading the desired rds pi and pty codes and up to 12 8-byte ps character strings. the si4711 will transmit the pi code and rotate through the transmission of the ps character strings with no further control required from outside the device. the second mode allows for more complicated transmissions. the pi and pty codes are written to the device as in mode 1. the remaining blocks (b, c, and d) are written to a 252 byte buffer. this buffer can hold 42 sets of bcd blocks. the si4711 creates rds groups by creating block a from the pi code, concatenating blocks bcd from the buffer, and rotating through the buffer. the bcd buffer is circular; so, the pattern is repeated until the buffer is changed. finally, the third mode allows the outside controller to burst data in to the bcd buffer, which emulates a fifo. the data does not repeat, but, when the buffer is nearly empty, the si4711 signals the outside device to initiate another data burst. this mode permits the outside device to use any rds functionality (including open data applications) that it wants. *note: rds/rbds is referred to only as rds throughout the remainder of this document. 5.9. tuning the frequency synthesizer uses silicon laboratories? proven technology including a completely integrated vco. the frequency synthesizer generates the quadrature local oscillator si gnal used to upconvert the low intermediate frequency to rf. the vco frequency is locked to the reference clock and adjusted with an automatic frequency control (afc) servo loop during transmission. the tuning frequency can be directly programmed with commands. for example, to tune to 98.1 mhz, the user writes the tx_tune_freq command with an argument = 9810. the si4710/11 supports channel spacing of 50, 100, or 200 khz. 5.10. reference clock the si4710/11 reference clock is programmable, supporting rclk frequencies from 31.130 khz to 40 mhz. the rclk frequency divided by an integer number (the prescaler value) must fall in the range of 31,130 to 34,406 hz. therefore, the range of rclk frequencies is not continuous below frequencies of 311.3 khz. the default rclk frequency is 32.768 khz. please refer to ?an332: universal programming guide? for using other rclk frequencies. 5.11. control interface a serial port slave interface is provided; this allows an external controller to send commands to the si4710/11 and receive responses from the device. the serial port can operate in three bus modes: 2-wire mode, spi mode, or 3-wire mode. the si4710/11 selects the bus mode by sampling the state of the gpo1 and gpo2/int pins on the rising edge of rst . the gpo1 pin includes an internal pull-up resistor that is connected while rst is low, and the gpo2/int pin includes an internal pull-down resistor that is connected while rst is low. therefore, it is only necessary for the user to actively drive pins that differ from these states.
si4710/11-b30 26 rev. 1.1 after the rising edge of rst , the pins, gpo1 and gpo2/int , are used as general-purpose output (o) pins as described in section ?5.12. gpo outputs?. in any bus mode, commands may only be sent after v io and v dd supplies are applied. 5.11.1. 2-wire control interface mode when selecting 2-wire mode, the user must ensure that sclk is high during the rising edge of rst , and stays high until after the first start condition. also, a start condition must not occur within 300 ns before the rising edge of rst . 2-wire bus mode uses only the sclk and sdio pins for signaling. a transaction begins with the start condition, which occurs when sdio falls while sclk is high. next, the user drives an 8-bit control word serially on sdio, which is captur ed by the device on rising edges of sclk. the control word consists of a seven bit device address followed by a read/write bit (read = 1, write = 0). the si4710/11 acknowledges the control word by driving sdio low on the next falling edge of sclk. although the si4710/11 responds to only a single device address, this address can be changed with the sen pin (note that the sen pin is not used for signaling in 2-wire mode). when sen = 0, the seven-bit device address is 0010001. when sen = 1, the address is 1100011. for write operations, the user then sends an eight bit data byte on sdio, which is captured by the device on rising edges of sclk. the si4710/11 acknowledges each data byte by driving sdio low for one cycle, on the next falling edge of sclk. the user may write up to eight data bytes in a single two-wire transaction. the first byte is a command, and the next seven bytes are arguments. for read operations, after the si4710/11 has acknowledged the control byte , it drives an eight-bit data byte on sdio, changing the state of sdio on the falling edge of sclk. the us er acknowledges each data byte by driving sdio low for one cycle, on the next falling edge of sclk. if a data byte is not acknowledged, the transaction ends. the user may read up to 16 data bytes in a single two-wire transaction. these bytes contain the response data from the si4710/11. a 2-wire transaction ends with the stop condition, which occurs when sdio rises while sclk is high. for details on timing specific ations and diagrams, refer to table 5, ?2-wire control interface characteristics 1,2,3 ,? on page 7, figure 2, ?2-wire control interface read and write timing parameters,? on page 8, and figure 3, ?2-wire control interface read and write timing diagram,? on page 8. 5.11.2. spi control interface mode when selecting spi mode, the user must ensure that a rising edge of sclk does not occur within 300 ns before the rising edge of rst . spi bus mode uses the sclk, sdio, and sen pins for read/write operations. for re ads, the user can choose to receive data from the device on either sdio or gpo1. a transaction begins when the user drives sen low. the user then pulses sclk eight times while driving an 8-bit control byte (msb first) serially on sdio. the device captures the data on rising edges of sclk. the control byte must have one of these values: 0x48 = write eight command/argument bytes (user drives write data on sdio) 0x80 = read status byte (device drives read data on sdio) 0xa0 = read status byte (device drives read data on gpo1) 0xc0 = read 16 response byte s (device drives read data on sdio) 0xe0 = read 16 response bytes (device drives read data on gpo1) when writing a command, after the control byte has been written, the user must drive exactly eight data bytes (a command byte and seven argument bytes) on sdio. the data will be captur ed by the device on the rising edges of sclk. after all eight data bytes have been written, the user raises sen after the last falling edge of sclk to end the transaction. in any bus mode, before sending a command or reading a response, the user must first read the status byte to ensure that the device is ready (cts bit is high). in spi mode, this is done by sending control byte 0x80 or 0xa0, followed by reading a single byte on sdio or gpo1. the si4710/11 changes the state of sdio or gpo1 after the falling edges of sclk. data should be captured by the user on the rising edges of sclk. after the status byte has been read, the user raises sen after the last falling edge of sc lk to end the transaction. when reading a response, the user must read exactly 16 data bytes after send ing the control byte. it is recommended that the user keep sen low until all bytes table 15. bus mode select on rising edge of rst bus mode gpo1 gpo2/int 2-wire 1 0 spi 1 1 (must drive) 3-wire 0 (must drive) 0
si4710/11-b30 rev. 1.1 27 have transferred. howeve r, it will not disrupt the protocol if sen temporarily goes high at any time, as long as the user does not change the state of sclk while sen is high. after 16 bytes have been read, the user raises sen after the last falling edge of sclk to end the transaction. at the end of any spi transa ction, the user must drive sen high after the final falling edge of sclk. at any time during a transaction, if sen is sampled high by the device on a rising edge of sclk, the transaction will be aborted. when sen is high, sclk may toggle without affecting the device. for details on timing specifications and diagrams, refer to figure 6 and figure 7 on page 10. 5.11.3. 3-wire control interface mode when selecting 3-wire mode, the user must ensure that a rising edge of sclk does not occur within 300 ns before the rising edge of rst . 3-wire bus mode uses the sclk, sdio and sen pins. a transaction begins when the system controller drives sen low. next, the system controller drives a 9-bit control word on sdio, which is captured by the device on rising edges of sclk. the control word is comprised of a three bit chip address (a7:a5 = 101b), a read/write bit (write = 0, read = 1), the chip address (a4 = 0), and a four bit register address (a3:a0). for write operations, the cont rol word is followed by a 16-bit data word, which is captured by the device on rising edges of sclk. for read operations, the cont rol word is followed by a delay of one-half sclk cycle for bus turnaround. next, the si4710/11 drives the 16-bit read data word serially on sdio, changing the state of sdio on each rising edge of sclk. a transaction ends when the user sets sen high, then pulses sclk high and low one final time. sclk may either stop or continue to toggle while sen is high. in 3-wire mode, commands are sent by first writing each argument to register(s) 0xa1?0xa3, then writing the command word to register 0xa0. a response is retrieved by reading registers 0xa8?0xaf. for details on timing specifications and diagrams, refer to table 6, ?3-wire control in terface characteristics,? on page 9, figure 4, ?3-wire control interface write timing parameters,? on page 9, and figure 5, ?3-wire control interface read timing parameters,? on page 9. 5.12. gpo outputs the si4710/11 provides three general-purpose output pins. the gpo pins can be configured to output a constant low, constant high, or high-z. the gpo pins are multiplexed with the bus mode pins or dclk depending on the applicat ion schematic of the transmitter. gpo2/int can be configured to provide interrupts. 5.13. reset, power up, and powerdown setting the rst pin low will disable analog and digital circuitry, reset the registers to their default settings, and disable the bus. setting the rst pin high will bring the device out of reset and place it in powerdown mode. a powerdown mode is available to reduce power consumption when the part is idle. putting the device in powerdown mode will disable analog and digital circuitry and keep the bus active. for more information concerning reset, powerup, powerdown, and initialization, refer to ?a n332: universal programming guide?. 5.14. programmi ng with commands to ease development time and offer maximum customization, the si4710/11 provides a simple yet powerful software interface to program the transmitter. the device is programmed using commands, arguments, properties, and responses. to perform an action, the user writes a command byte and associated arguments causing the chip to execute the given command. command s control actions, such as powering up the device, shutting down the device, or tuning to a station. arguments are specific to a given command and are used to modify the command. for example, after the tx_tune_freq command, arguments are required to set the tune frequency. a complete list of commands is available in table 16, ?si471x command summary,? on page 28. properties are a special command argument used to modify the default chip operation and are generally configured immediately after powerup. examples of properties are tx_preemphasis and gpo_configure. a complete list of properties is available in table 17, ?si471x property summary,? on page 29. responses provide the user information and are echoed after a command and associated arguments are issued. at a minimum, all commands provide a one-byte status update indicating interrupt and clear-to-send status information. for a detailed description of using the commands and properties of the si4710/11, see ?an332: universal programming guide.?
si4710/11-b30 28 rev. 1.1 6. commands and properties table 16. si471x command summary cmd name description 0x01 power_up power up device and mode selection. modes include fm transmit and analog/digital audio interface configuration. 0x10 get_rev returns revision information on the device. 0x11 power_down power down device. 0x12 set_property sets the value of a property. 0x13 get_property retrieves a property?s value. 0x14 get_int_status read interrupt status bits. 0x15 patch_args reserved command us ed for patch file downloads. 0x16 patch_data reserved command used for patch file downloads. 0x30 tx_tune_freq tunes to given transmit frequency. 0x31 tx_tune_power sets the output power level and tunes the antenna capacitor 0x33 tx_tune_status queries the status of a previously sent tx tune freq, tx tune power, or tx tune measure command. 0x34 tx_asq_status queries the tx status and input audio signal metrics. 0x35 tx_rds_buff si4711 only . queries the status of the rds group buffer and loads new data into buffer. 0x36 tx_rds_ps si4711 only . set up default ps strings. 0x80 gpo_ctl configures gpo3 as output or hi-z. 0x81 gpo_set sets gpo3 output level (low or high).
si4710/11-b30 rev. 1.1 29 table 17. si471x property summary prop name description default 0x0001 gpo_ien enables interrupt sources. 0x0000 0x0101 digital_input _format configures the digital input format. 0x0000 0x0103 digital_input _sample_rate configures the digital input sa mple rate in 10 hz steps. default is 0. 0x0000 0x0201 refclk_freq sets frequency of the reference clock in hz. the range is 31130 to 34406 hz, or 0 to disable the afc. default is 32768 hz. 0x8000 0x0202 refclk_prescale sets the prescaler value for the reference clock. 0x0001 0x2100 tx_component_enable enable transmit multip lex signal components. default has pilot and l-r enabled. 0x0003 0x2101 tx_audio_deviation configures audio frequency deviation level. units are in 10 hz increments. default is 6285 (68.25 khz). 0x1aa9 0x2102 tx_pilot_deviation configures pilot tone frequency deviation level. units are in 10 hz increments. default is 675 (6.75 khz) 0x02a3 0x2103 tx_rds_deviation si4711 only. configures the rds/rbds frequency deviation level. units are in 10 hz increments. default is 2khz. 0x00c8 0x2104 tx_line_input_level configures maximum analog line input level to the lin/rin pins to reach the maximum deviation level pro- grammed into the audio deviation property tx audio deviation. default is 636 mv pk . 0x327c 0x2105 tx_line_input_mute sets line input mute. l and r inputs may be indepen- dently muted. default is not muted. 0x0000 0x2106 tx_preemphasis configures pre-emphasis time constant. default is 0 (75 s). 0x0000 0x2107 tx_pilot_frequency configures the frequency of t he stereo pilot. default is 19000 hz. 0x4a38 0x2200 tx_acomp_enable enables audio dynamic range control. default is 0 (disabled). 0x0002 0x2201 tx_acomp_threshold sets the threshold level for audio dynamic range control. default is ?40 db. 0xffd8 0x2202 tx_acomp_attack_time sets the attack time for audio dynamic range control. default is 0 (0.5 ms). 0x0000 0x2203 tx_acomp_release_time sets the release time for audio dynamic range control. default is 4 (1000 ms). 0x0004 0x2204 tx_acomp_gain sets the gain for audio dynamic range control. default is 15 db. 0x000f 0x2205 tx_limiter_release_time sets the limiter release time. default is 102 (5.01 ms) 0x0066 0x2300 tx_asq_int errupt_source configures measurements related to signal quality met- rics. default is none selected. 0x0000 0x2301 tx_asq_level_low configures low audio input level detection threshold. this threshold can be used to detect silence on the incoming audio. 0x0000
si4710/11-b30 30 rev. 1.1 0x2302 tx_asq_duration_low configures the duration which the input audio level must be below the low threshold in order to detect a low audio condition. 0x0000 0x2303 tx_asq_level_high configures high audio input level detection threshold. this threshold can be used to detect activity on the incoming audio. 0x0000 0x2304 tx_asq_duration_high configures the duration which the input audio level must be above the high threshold in order to detect a high audio condition. 0x0000 0x2c00 tx_rds_interrupt_source si4711 only. configure rds interrupt sources. default is none selected. 0x0000 0x2c01 tx_rds_pi si4711 only. sets transmit rds program identifier. 0x40a7 0x2c02 tx_rds_ps_mix si4711 only. configures mix of rds ps group with rds group buffer. 0x0003 0x2c03 tx_rds_ps_misc si4711 only. miscellaneous bits to transmit along with rds_ps groups. 0x1008 0x2c04 tx_rds_ps_repeat_count si4711 only. number of times to repeat transmission of a ps message before transmitting the next ps mes- sage. 0x0003 0x2c05 tx_rds_ps_ message_count si4711 only. number of ps messages in use. 0x0001 0x2c06 tx_rds_ps_af si4711 only. rds program serv ice alternate fre- quency. this provides the abilit y to inform the receiver of a single alternate frequency using af method a coding and is transmitted along with the rds_ps groups. 0xe0e0 0x2c07 tx_rds_fifo_size si4711 only. number of blocks reserved for the fifo. note that the value written must be one larger than the desired fifo size. 0x0000 table 17. si471x property summary (continued) prop name description default
si4710/11-b30 rev. 1.1 31 7. pin descriptions: si4710/11-gm pin number(s) name description 1, 2, 20 nc no connect. leave floating. 3 rfgnd rf ground. connect to ground plane on pcb. 4 txo fm transmit output connection to transmit antenna. 5 rst device reset (active low) input. 6 sen serial enable input (active low). 7 sclk serial clock input. 8 sdio serial data input/output. 9 rclk external refere nce oscillator input. 10 v io i/o supply voltage. 11 v dd supply voltage. may be connected directly to battery. 13 din digital input data. 14 dfs digital frame synchronization input. 15 rin right audio line input. 16 lin left audio line input. 17 gpo3/dclk general purpose output/digital bit synchronous clock input. 18 gpo2/int general purpose output/interrupt request. 19 gpo1 general purpose output. 12, gnd pad gnd ground. connect to ground plane on pcb. gnd pad 1 2 3 17 18 19 20 11 12 13 14 6 7 8 9 4 5 16 10 15 gpo2/int vio rin dfs din gnd rst nc txo rclk sdio vdd nc rfgnd gpo3/dclk nc gpo1 lin sclk sen
si4710/11-b30 32 rev. 1.1 8. ordering guide part number* description package type operating temperature si4710-b30-gm portable broadcast fm transmitter qfn pb-free ?20 to 85 c SI4711-B30-GM portable broadcast fm transmitter with rds/rbds encoder qfn pb-free ?20 to 85 c *note: add an ?(r)? at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
si4710/11-b30 rev. 1.1 33 9. package markings (top marks) 9.1. si4710 top mark figure 19. si4710 top mark 9.2. si4711 top mark figure 20. si4711 top mark 9.3. top mark explanation mark method: yag laser line 1 marking: part number 10 = si4710 11 = si4711 firmware revision 30 = firmware revision 30 line 2 marking: r = die revision b = revision b die ttt = internal code internal tracking code. line 3 marking: circle = 0.5 mm diameter (bottom-left justified) pin 1 identifier y = year ww = workweek assigned by the assembly house. corresponds to the last sig- nificant digit of the year and workweek of the mold date.
si4710/11-b30 34 rev. 1.1 10. package outline: si4710/11-gm figure 21 illustrates the packag e details for the si4710/11. table 18 lists the values for the dimensions shown in the illustration. figure 21. 20-pin quad flat no-lead (qfn) table 18. package dimensions symbol millimeters symbol millimeters min nom max min nom max a 0.50 0.55 0.60 f 2.53 bsc a1 0.00 0.02 0.05 l 0.35 0.40 0.45 b 0.200.250.30 l1 0.00 ? 0.10 c 0.27 0.32 0.37 aaa ? ? 0.05 d 3.00 bsc bbb ? ? 0.05 d2 1.65 1.70 1.75 ccc ? ? 0.08 e 0.50 bsc ddd ? ? 0.10 e 3.00 bsc eee ? ? 0.10 e2 1.65 1.70 1.75 notes: 1. all dimensions are shown in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994.
si4710/11-b30 rev. 1.1 35 11. pcb land pattern: si4710/11-gm figure 22 illustrates the pcb land patter n details for the si4710/11-gm. table 1 9 lists the values for the dimensions shown in the illustration. figure 22. pcb land pattern
si4710/11-b30 36 rev. 1.1 table 19. pcb land pattern dimensions symbol millimeters symbol millimeters min max min max d 2.71 ref ge 2.10 ? d2 1.60 1.80 w ? 0.34 e 0.50 bsc x ? 0.28 e 2.71 ref y 0.61 ref e2 1.60 1.80 ze ? 3.31 f 2.53 bsc zd ? 3.31 gd 2.10 ? notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. this land pattern design is based on ipc-sm-782 guidelines. 4. all dimensions shown are at maximum mate rial condition (mmc ). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. note: solder mask design 1. all metal pads are to be non-solder-ma sk-defined (nsmd). clearance between the solder mask and the metal pad is to be 60 mm minimum, all the way around the pad. notes: stencil design 1. a stainless steel, laser-cut and electro-po lished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads. 4. a 1.45 x 1.45 mm square aperture should be used for the center pad. this provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component standoff. notes: card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si4710/11-b30 rev. 1.1 37 12. additional reference resources si47xx-evaluation board user?s guide an309: si4710/11/12/13 evaluation board quick-start guide an332: universal programming guide an383: universal antenna selection and layout guidelines an388: universal evaluation board test procedure si4710/11/12/13 customer suppor t site: http://www.mysilabs.com this site contains all application notes, evaluation b oard schematics and layouts, and evaluation software. nda is required for access. to request access, send mysilabs user name and request for access to fminfo@silabs.com.
si4710/11-b30 38 rev. 1.1 n otes :
si4710/11-b30 rev. 1.1 39 d ocument c hange l ist revision 0.5 to revision 1.1 updated table 9 on pages 12 and 13 corrected typo in section 5.3.2 on page 21. updated references to new application notes throughout document. updated table 3 on page 5. updated production test condition in table 9 on page 12.
si4710/11-b30 40 rev. 1.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: fminfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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